Cap Dump Circuit using High-Sided Switching

[JulesP]

I have modified a design for a capacitor capture circuit that recycles BackEMF pulses by charging a large capacitor and periodically discharging it to one or other of two lead-acid batteries. (The reason why there are two batteries is that at any moment one of them is also receiving the BackEMF pulses directly and these batteries don’t like providing charge for the main circuit and simultaneously receiving these pulses).

The intended circuit operation is this: when capacitor C1 reaches a voltage set by the adjustment trimmer R3, it allows the LM741 to trigger an optoisolator which then operates a P channel FET (Q2). As a high-sided switch, this lets through the pulse, at say 15V, to one or other of two P channel FETs (Q5 and Q6) which are on or off depending on the ‘battery switching’ logic provided by another part of the circuit (either output 1 or 2 is a 12V high). Therefore one of these two FETs will pass on the pulse to one or other of the batteries.

The discharging capacitor will stop releasing its charge when its voltage drops to about 9V and this value, the hysteresis, can be adjusted with trimmer R6.

My query then is about whether the way I have set up the three ‘high sided’ switching FETs will work as intended (the original design used two N channel FETs in parallel for low-sided switching), or if I need to include any additional components, or perhaps different values of those already included, or modify the circuit.

Thanks

[Gary Hammond]

Hi Jules,

(The reason why there are two batteries is that at any moment one of them is also receiving the BackEMF pulses directly and these batteries don’t like providing charge for the main circuit and simultaneously receiving these pulses).

I'm not sure I understand what you're trying to accomplish. Are you running an SSG machine from first one battery and then the other one with automatic switching while charging the one not running the machine with the cap capture circuit?

Looking at your schematic, I don't see how any BackEMF gets to either battery during the cap charging phase except for the small amount that always feeds back to the run battery reducing it's current draw. And I don't see any connections between either battery and the SSG run circuit, which I assume, would require isolation diodes to keep the two batteries separated.

The intended circuit operation is this: when capacitor C1 reaches a voltage set by the adjustment trimmer R3, it allows the LM741 to trigger an optoisolator which then operates a P channel FET (Q2).

Because the gate of Q2 is tied directly to the 15 volt reference zener D5, any time the capture cap exceeds 15 volts, Q2 will trigger and start to dump the cap. If the reference voltage pot R3 is set to trigger the optoisolator above 15 volts it can't control the gate of Q2 because it will already be turned on.by the D5 reference voltage. And if the R3 pot is set to trigger the optoisolator before the Cap reaches 15 volts, the TIP41C will trigger on, thus dropping the gate voltage of Q2 as well as the reference voltage to about 1 or 1.5 volts. Since this is also the input operating voltage for the op-amp, it will not operate properly and let the optoisolator turn the transistor off rapidly regardless of the hysteresis setting. This will probably set up a high frequency oscillation of the trigger circuit, if I'm thinking correctly.

I think that in order to work correctly the TIP41C that is turned on by the optoisolator needs to be between R10 and another added independent 2K2 resistor going from the collector to the RED high voltage charging cap lead. Then the gate of Q2 should be connected to the collector of the TIP41C and not to the 15 volt zener reference. The trigger circuit has to be isolated from the cap dump circuit by the optoisolator to prevent unwanted feed back.

This should allow you to charge the cap to 24 volts and set the hysteresis pot to stop the dump at 17 volts, which are the proper voltages. (Turning the dump on at 15 volts and off at 9 volts would not be able to charge the battery.)

For some reason John Bedini always preferred low side switching to high side switching. He thought it gave slightly better or faster charging for some reason having to do with the inertia of charge carriers in the battery, as best I can recall. But either method should work.

Gary Hammond,

[JulesP]

Hi Gary,

Good to hear from you again. Long time no chat! I hope you have been keeping well during these times of considerable upheaval and change.

After doing a lot of work on a rotor based unit several years back (see the pic of my original 'Phase 1' design) and a subsequent solid-state device that you gave me a lot of help on, I have returned to the rotor based unit to work on a series of upgrades with the aim of obtaining some better and more conclusive results; all part of the inductive method of replicating an observed phenomenon.

Among the planned improvements in 'Phase 2' are replacing all my 'shoestring' circuitry with a dedicated PCB (pic), driving the main FET with a driver chip circuit (pic) to give a faster FET shutoff, on the basis that a greater dV/dt will increase the BackEMF from its present 800V to over 1000V, an internal timer-based trigger circuit as an alternative to the external Hall sensor and an inbuilt rev counter. I am including plenty of test points for diagnostics and am now in the early stages of building this but, as always, I'm thinking ahead to Phase 3 (well the garden doesn't need mowing) which will include a switchable cap dump circuit and, further ahead, some inductive means to tap off the energy of the rotor (spinning at 2,500-3,000rpm) to add to the battery or output load.

The circuit I showed in the first post does not display the battery swapper in any detail and which serves to direct the HV pulses to the battery that is not running the circuit at that time and switching them over every 30 to 300 seconds. It's been a recent habit of mine on more conventional forums to keep the subject matter tight to avoid question drift and confusion but I must remember here that everything is recognised, understood and respected

So here I include my latest version of the battery swapper circuit (pic) with the only real change from the one I built 3 years ago being to switch from using TIP3055s to STP40NF03L FETs for the main switching devices. Using these N channel devices as high sided switches, as with the previous BJTs, will lose me part of a volt but that's not critical to the main circuit running. For the cap dump circuit, I propose using the FET Gate feeds from the battery swapper to provide the 'battery switching logic' referred to in that circuit to direct the cap pulses to the right battery. So my intention in 'Phase 3' is to have the HV pulses go to either the cap dump circuit or the battery swapper or both in parallel for some comparison experiments.

I agree that low sided switching is easier and where, in the original cap dump circuit this is what is used, in my case my circuit topology is different and the cap dump is not part of its original design and so with there being a permanent and direct connection of the batteries to Ground, that would bypass the FETs so making 'low side switching' not possible.

I will go through your circuit suggestions and make the modifications and repost the circuit together with some inevitable questions. Given that I need to use P channel FETs whose Gates are grounded to turn them on, I think I should also add some 'pull up' resistors at their gates to ensure they turn off.

While over the last 4 or so years I have learned a lot about circuits, I'm not overly confident in my thought processes when it comes to designing them and so appreciate the input of those like yourself who have much more experience. On the other hand, if you want a good photo taken or a wooden bowl made from a log then I'm your man


Jules

[JulesP]

Hi Gary,

Here is the revised cap dump circuit with your suggested adjustments. I have also added a pull-up resistor for each of the three FETs (Q2,5&6) to ensure they switch off when the low signal is removed from their Gates.

To make things clearer with regard to how this circuit integrates with other circuit elements, I have shown not all but the main elements of the battery swapper. As it is shown, when battery 1 is powering the circuit, the HV pulses and the cap dump discharges will be routed to battery 2 and this will switch over at a preset interval.

I have a few questions regarding the revised circuit:

Is the 15V Zener D5 now only serving to maintain a stable 15V for the op-amp and the optoisolator? Similarly D3 for the Hysteresis adjustment? In the original cap pulser (see pic) a 15V Zener was also connected to the emitter of the BJT immediately after the optoisolator, in other words differently from how I had it. Perhaps it's not needed in my 'high-sided switch' version.

With the voltage on C1 able to reach 24V, will any of the components need to be protected from that increase, such as Q1 and Q4, and should the value of R15 be increased to 2k2 also?

Thank you,

Jules

[Gary Hammond]

Hi Jules,

I wasn't very clear in my suggestions on how to modify your circuit. What you have drawn is not totally correct. If I can figure out how to redraw your schematic I'll post it back in this thread. I don't know any good way to turn your JPEG image into any of my drawing programs so I can modify it to show you what I was suggesting.

Give me a couple of days to work on it and maybe I can figure out how to do it.

I'll try a verbal explanation again. Looking at your new schematic, the biasing on Q1 and the optocoupler are incorrect. The opto pin#5 should be connected to the Q1 collector and R13 junction. (Opto pin #5 cannot be connected to the opto pin# 1).

Totally eliminate R11. ............ R13 pulls the Q2 base high until the Q1 transistor pulls it back low through R10.

These changes should make it work.

Is the 15V Zener D5 now only serving to maintain a stable 15V for the op-amp and the optoisolator?

Yes. That is correct.

Similarly D3 for the Hysteresis adjustment?

Yes. That is correct.

In the original cap pulser (see pic) a 15V Zener was also connected to the emitter of the BJT immediately after the optoisolator, in other words differently from how I had it. Perhaps it's not needed in my 'high-sided switch' version.

I don't know why it's there. I didn't use it in my cap dump at all, and it works just fine. I also didn't use the R12 100K stabilization resistor in mine.

With the voltage on C1 able to reach 24V, will any of the components need to be protected from that increase, such as Q1 and Q4

I don't think that will be a problem.

and should the value of R15 be increased to 2k2 also?

Yes, I would change both R9 and R15 to 2k2 so that when the transistors turn on, the outputs to the bases of Q5 and Q6 go lower.

Gary Hammond,

[JulesP]

Thanks Gary. I don’t want to put you to too much trouble trying to convert my screen grabs to a user friendly form. I do these in Keynote on a Mac and then when they are correct I go to EasyEDA online to draw up a schematic which I can then convert to a PCB.

I will try again to make the correct changes. I’m not short of time!

[JulesP]

One option might be for me to draw up that section of the circuit using EasyEDA and share that with you by saving it in a format you can import. I know it can export a .json file as a backup so maybe that is a format you can work with?

[JulesP]

Gary, you can see my confusion when in this circuit by RS_ opto pin 1 is connected to opto pin 5

[Gary Hammond]

Hi Jules,

That particular schematic was for 24 to 36 volt systems.

Here's a link to RS's schematic for 12 volt systems. https://www.energyscienceforum.com/f...9856#post19856

And here's a link to where he explains the function of the 15v zener. It is used to keep the gate voltage from going over 15 volts.
https://www.energyscienceforum.com/forum/alternative-energy/john-bedini/bedini-sg-official-monopole-forum/1084-bedini-comparator-cap-dump?p=20094#post20094

I may have misspoken when I said I didnt use that zener. I may have used it. Been so long since I built it that I don't remember for sure. LOL. I just completed my 80th orbit around the sun last week and am starting my 81st orbit.

Gary Hammond,

[JulesP]

Well that’s an achievement! Well done. I’m not far off 66 and about to collect my state pension

So I should probably add another Zener for the gate of my Q2?

Do you know if you can import .Json files into your schematic programme? If so I can draw part of the circuit and send that over to you to tweak. But it’s now time here.

Jules

[Gary Hammond]

Hi Jules,

I've never heard of .Json files, so I doubt it. I was,however, able to modify your JPEG photo with paint. I'll see if I can get it to upload.

So I should probably add another Zener for the gate of my Q2?

I'm not sure it's needed or even where to put it. Maybe in parallel with R13?

Gary Hammond,

[JulesP]

Hi Gary,

Thanks for doing that. Good old Paint.

Regarding the use of another Zener, I agree that there is little or no value in holding the collector of Q1 at 15V, when the supply line is climbing to 24V, by connecting a Zener between the collector and ground. The TIP41C can accommodate up to 100V.

Correct me if I’m wrong but without a Zener the voltage of Q1’s collector will rise to 24V while Q1 is off and then drop instantly to zero when it turns on; and hence turn on Q2?

I will revise my circuit as you have done.

Thanks again and I will update you and this thread on how the Phase 1 upgrades go and any meaningful results.

Jules

[Gary Hammond]

Hi Jules,

Good old Paint.

I don't use paint very often and have trouble getting it to do what I want.

Regarding the use of another Zener, I agree that there is little or no value in holding the collector of Q1 at 15V, when the supply line is climbing to 24V, by connecting a Zener between the collector and ground. The TIP41C can accommodate up to 100V.

The zener would go between the collector and the capture cap voltage (in parallel with R13). This is not to protect the Tip41 transistor Q1, but rather would prevent the gate voltage on Q2 from dropping more than 15 volts below the source voltage (capture cap voltage).

Correct me if I’m wrong but without a Zener the voltage of Q1’s collector will rise to 24V while Q1 is off and then drop instantly to zero when it turns on; and hence turn on Q2?

Without the zener both the Q2 gate and the Q1 collector voltages would drop to approximately R10/R13 x cap voltage (220/2200 x 24 = 2.4 volts) at the beginning of cap discharge. It would then drop to about 220/2200 x 17 = 1.7 volts at the end of cap discharge. These are in reference to ground voltage which is not what we are concerned about.

With the zener installed, both the Q2 gate and the Q1 collector would drop to capture cap voltage minus the zener voltage. At the beginning of cap discharge this would be 24 - 15 = 9 volts and at the end of discharge it would be 17 - 15 = 2 volts above ground. But the voltage to ground is not what we are trying to limit, but rather the voltage between the source and gate of the FET Q2 !!

With the zener installed the source to gate voltage would be a maximum of 15 volts throughout the entire cap dump event. Without the zener it could reach 24 - 2.4 = 21.6 volts. If the Q2 (Si3421DV FET) can withstand this high of a voltage between the source and gate, then the zener wouldn't be required. This doesn't take into consideration any di/dt impulse resulting from the rapid current flow at discharge. So, it might still be wise to include the zener.

Gary Hammond,

[JulesP]

Thank you Gary for the detailed analysis.

The Q2 FET can withstand a Vgs of +_ 20V and a Vds of -30V (see pic) so on that basis it would be best to include the Zener.

I’m not sure how much the Q2 Gate voltage has to drop to turn on. From the spec sheet is that the -4.5 to -10V related to Rds in the summary box at the top? So I’m hoping that the 9V and 2V you calculated will be ok to keep it on?

Jules
8350BBA6-8741-4472-BA15-0872FA4F7A12.png

[Gary Hammond]

Hi Jules,

I’m not sure how much the Q2 Gate voltage has to drop to turn on. From the spec sheet is that the -4.5 to -10V related to Rds in the summary box at the top? So I’m hoping that the 9V and 2V you calculated will be ok to keep it on?

The gate to ground voltage isn't what keeps Q2 on, so no need to worry about it. The gate to source voltage (V_gs ) is what turns on the FET and keeps it on. This is limited to 15 volts all the time the Q1 is on when the zener is included as shown in the last schematic. And V_gs without the zener would be 21.6 to 15.3 volts. This is well above the 4.5 to 10 volts you indicated. I guess these are all listed as negative voltages because they are in reference to the source, i.e. the capture cap.

The spec sheet you posted is so small I can't read it.

Gary Hammond,